Analog Circuit Design - High-Speed Clock And Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier PDF

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

ISBN-10: 1402089430

ISBN-13: 9781402089435

Analog Circuit layout comprises the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and invaluable layout principles within the sector of analog circuit layout. each one half is gifted via six specialists in that box and cutting-edge details is shared and overviewed. This publication is quantity 17 during this profitable sequence of Analog Circuit layout.

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M. Meghelli, S. , “A 10 Gb/s 5-Tap-DFE-4-Tap-FFE transceiver in 90 nm CMOS”, ISSCC Dig. of Tech. Papers, pp. 80–81, Feb. 2006. 4. K. J. Wong, C. K. Yang, “A Serial-Link Transceiver with Transition Equalization”, ISSCC Dig. of Tech. Papers, pp. 82–83, Feb. 2006. 5. Fibre Channel, “Physical Interface-4 (FC-PI-4)”, Int. Committee for Information Technology Standardization (INCITS), Rev. 7, Sept. 2007. 6. R. Kajley, P. Hurst, “A Mixed-Signal Decision-Feedback Equalizer That Uses a Look-Ahead Architecture”, IEEE J.

4 shows a common implementation of a boost equalizer as a cascade of CML zero-pole high pass stages. In this case, the equalizer has been designed to match the channel reverse function at low frequencies. If the Nyquist boost is increased, data patterns alternating opposite bits (clock patterns) will be better equalized, but in case the channel reverse function is not matched at lower frequencies, the overall vertical eye opening can not be improved. As shown in the example of Fig. 5, increasing the boost at Nyquist improves the vertical eye opening, until a maximum level is reached.

One possible way of linearizing the bang-bang detector is to add extra levels to it as shown in Fig. 5. In this case, the magnitude of the phase error can be sensed in addition to its sign, though only in discrete intervals which are set by the delay of the buffers shown in the figure. In the case where the input data signal has sufficient jitter to exercise the various levels of this detector, the CDR dynamics will be behave in a reasonably linear manner such that the jitter transfer characteristic becomes well defined.

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Analog Circuit Design - High-Speed Clock And Data Recovery, High-Performance Amplifiers, Power Management by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier


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